Dram Testing Using Interleaving Test Algorithm

For more than four decades, the simple structure of the dynamic RAM (DRAM) cell and continuous improvement in lithography and dry-etching technology has made DRAM grow exponentially in a large-scale integration and has decreased the minimum feature size in memory chips. In the field of testing, more appropriate test algorithms are required to protect DRAM cell data.In this paper an Interleaving test algorithm is presented, which requires a read time of 110μs. This test algorithm allows screening of weak cells that cannot hold cell data due to the sub threshold leakage current with a screen coverage of 35.2%. During the stress period, the algorithm can also detect other leakage currents.